Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

This paper discusses an approach to timing closure to eliminate non-determinism in an asynchronous interface while performing AC characterization on ATE (automatic test equipment). By closing the ...

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet ...

In the simulation and verification world, particularly with regard to system-on-a-chip (SoC) design closure, certain fault types have made their way to silicon with greater frequency. Many of today's ...

CMOS is, and will continue to be, the work-horse process technology of the semi-conductor industry. But designers of large devices, of complex SoCs and of devices using multiple IP elements are ...

Today's leading-edge system-on-chip (SoC) designs typically have multiple clock domains and, in many cases, multiple internally generated clocks. In test mode, those clocks may be combined into one, ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

Clock domain crossings are significant sources of field system failures. Despite this fact, designs continue to be released without fully verified CDCs. A false sense of security resulting from ...