BizTech

What Is a Field Programmable Gate Array and How Does It Work?

Ernie Smith is a former contributor to BizTech, an old-school blogger who specializes in side projects, and a tech history nut who researches vintage operating systems for fun. When it comes to major ...
Electronic Design

Pioneering FPGA-on-Modules: SGET Works to Develop Standard

The SGET embedded standardization body is hammering out a standard for FPGA-on-modules. Discover the benefits and how the new Harmonized FPGA Module (HFM) standard will impact the industry. Why ...
Electronic Design

MathWorks speeds up FPGA-in-the-loop verification

Natick, MA. MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with the FPGA board and ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Network World

Altera targets AI edge with updates for its Agilex FPGA portfolio

To celebrate this transition, Altera used its annual Innovator’s Day developer conference as the backdrop for the news, ...