Semiconductor Engineering

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. “With the continuous miniaturization of ...
Business Wire

Onto Innovation Advances Process Control Suite for 3D Interconnect Yields

WILMINGTON, Mass.--(BUSINESS WIRE)--Onto Innovation Inc. (NYSE: ONTO) today announced advances in its product suite for 3D interconnect process control, featuring the new 3Di ™ technology on the ...
Semiconductor Engineering

Why Wafer Bumps Are Suddenly So Important

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing ...
EDN

Solder-bump technology breaks cooling, power-generation constraints

A potential breakthrough technology from Nextreme (Research Triangle Park, NC)—a microscale thermal and power-management device manufacturer—integrates cooling and power-generation capabilities into ...
EDN

Xilinx uses Unitive’s eutectic wafer-bumping process to lower FPGA costs

RESEARCH TRIANGLE PARK, N.C. — Flip-chip technology supplier Unitive Inc. here today announced qualification of its eutectic wafer-bumping process for volume production of high-density ...